Complementary Metal Oxide Semicondcutor (CMOS) low voltage amplifiers are used in a variety of circuit applications including consumer electronics, telecommunications, automotive, aviation, etc. Typically these amplifiers are connected in a feedback configuration to linearly amplify a voltage difference that appears at their inputs. Like other integrated circuits, CMOS low voltage amplifiers are described in terms of various performance parameters, e.g., common mode input voltage, common mode rejection ratio, gain, slew rate, full-power bandwidth, input resistance, and output resistance, among others. Common mode input voltage range is an important performance parameter that indicates the range of input voltages over which a differential amplifier behaves in a linear fashion, i.e., the range of input voltages over which the amplifier can operate without any of the circuits of the individual gain stages within the amplifier entering a saturation operating mode. Common mode rejection ratio (CMRR) is a related performance parameter that is defined as the ratio of the open loop gain of the CMOS low voltage amplifier to its common mode gain. This performance parameter is a measure of the operational amplifier's ability to reject input signals that are common to both of the operational amplifier's differential inputs.
For CMOS low voltage operational amplifiers, it is desirable to maintain a high common mode rejection ratio over a wide range of common mode input voltages. This is a challenging goal because the processes for manufacturing CMOS low voltage amplifiers are typically suited for building field effect transistors having high threshold voltages. FIG. 1 illustrates a prior art CMOS low voltage operational amplifier 10 manufactured using a 5 volt CMOS process for which the nominal threshold voltages of field effect transistors 20, 22, 30, 32, 34, and 36 are about 0.8 volts. CMOS low voltage operational amplifier 10 comprises a differential pair 12 of transistors coupled to a differential pair load 14 and to a current source 16. Differential pair 12 comprises P-channel metal oxide semiconductor field effect transistors (MOSFETS) 20 and 22, wherein the sources of P-channel MOSFETS 20 and 22 are commonly connected together and the gates are coupled for receiving input signals VIN+ and VIN−, respectively. In addition to input signals VIN+ and VIN−, the gates of P-channel MOSFETS 20 and 22 each receive a common mode input signal VCM. The sources of P-channel MOSFETS 20 and 22 are also electrically coupled to the body or bulk terminal 26 of the semiconductor material from which the operational amplifier is manufactured. The drains of P-channel MOSFETS 20 and 22 are coupled to differential pair load 14 which is coupled for receiving a source of operating potential VEE. By way of example, load 14 is a current mirror.
Current source 16 comprises P-channel MOSFETS 30, 32, 34, and 36 coupled in a cascode configuration, wherein the drain of P-channel MOSFET 32 is coupled to source of operating potential VEE through a current setting resistor 38, and the drain of P-channel MOSFET 36 is connected to the sources of P-channel MOSFETS 20 and 22. The sources of P-channel MOSFETS 30 and 34 are commonly coupled for receiving a source of operating potential VCC. The gates of P-channel MOSFETS 30 and 34 are connected together and to the drain of P-channel MOSFET 32. The gates of P-channel MOSFETS 32 and 36 are connected together and for receiving a bias voltage VBIAS. In operation, the maximum common mode input voltage VCM,MAX that can be applied to differential pair 12 is given by equation 1 (EQT. 1):VCM,MAX=VCC−(|Vtho|+2*Vdsat)  EQT. 1
where:                VCC is the upper supply or upper supply rail of the amplifier (volts);        Vtho is the threshold voltage with zero potential across the body and source terminals (volts); and        Vdsat is the saturation voltage for the P-channel MOSFET (volts).        
For a 5 volt CMOS process in which the upper supply rail is 1.8 volts and the saturation voltage for the P-channel MOSFETS is about 100 millivolts, the maximum common mode input voltage, VCM,MAX, is about 0.8 volts.
The minimum common mode input voltage VCM,MIN that can be applied to differential pair 12 is given by equation 2 (EQT. 2):VCM,MIN=VEE+VDIFFLD−|Vtho|  EQT. 2
where:                VEE is the lower supply or lower supply rail of the amplifier (volts);        VDIFFLD is the voltage drop across differential pair load 14 (volts); and        Vtho is the threshold voltage with zero potential across the body and source terminals (volts).        
For the 5 volt CMOS process in which the lower supply rail is 0 volts and the voltage drop across differential pair load 14 is about 100 millivolts, the minimum common mode input voltage, VCM,MIN, is about −0.5 volts. Thus, the common mode input voltage range is about 1.3 volts.
A drawback with this circuit is that techniques for increasing the maximum common mode input voltage VCM,MAX have also increased the minimum common mode input voltage VCM,MIN. Because both the maximum and minimum common mode input voltages are increased, the common mode input voltage range is not increased.
Another parameter that limits the common mode range of a circuit such as, for example, an operational amplifier, is the threshold voltages of the transistors making up the circuit. When the threshold voltages of these circuits are large, parameters such as common mode range are degraded. This limitation also applies to other analog and digital circuits.
Accordingly, it would be advantageous to have a circuit and a method for increasing the common mode input voltage range. In addition, it would be advantageous for the circuit and method to adjust the threshold voltages of the transistors in the circuit. It would be of further advantage for the circuit and method to be time and cost efficient to implement.